Development of plasma etching process for sub-50 nm TaN gate

@article{130, abstract = {TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl2, Cl2/BCl3/Ar, Cl2/BCl3, and Cl2/Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl2/Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10- 2 A/cm2 at gate bias of 1 V and absence of polysilicon depletion effect.}, author = {Bliznetsov, Vladimir and Kumar, Rakesh and Bera, Lakshmi K. and Yip, Loh W. and Du, Anyan and Hui, Tang E. }, booktitle = {Proceedings of The International Conference on Materials for Advanced Technologies (ICMAT 2005) Symposium H: Silicon Microelectronics:Processing to Packaging - ICMAT 2005 Symposium H}, citeulike-article-id = {2818328}, doi = {http://dx.doi.org/10.1016/j.tsf.2005.09.158}, journal = {Thin Solid Films}, keywords = {metal-gate, midgap, tan}, month = {May}, number = {1-2}, pages = {140--144}, posted-at = {2008-05-21 07:32:57}, priority = {2}, title = {Development of plasma etching process for sub-50 nm TaN gate}, url = {http://dx.doi.org/10.1016/j.tsf.2005.09.158}, volume = {504}, year = {2006} }

TY - JOUR ID - 130 L3 - citeulike-article-id:2818328 TI - Development of plasma etching process for sub-50 nm TaN gate T2 - Proceedings of The International Conference on Materials for Advanced Technologies (ICMAT 2005) Symposium H: Silicon Microelectronics:Processing to Packaging - ICMAT 2005 Symposium H JF - Thin Solid Films VL - 504 IS - 1-2 SP - 140 EP - 144 N2 - TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl2, Cl2/BCl3/Ar, Cl2/BCl3, and Cl2/Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl2/Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10- 2 A/cm2 at gate bias of 1 V and absence of polysilicon depletion effect. KW - metal-gate KW - midgap KW - tan AU - Bliznetsov, Vladimir AU - Kumar, Rakesh AU - Bera, Lakshmi AU - Yip, Loh AU - Du, Anyan AU - Hui, Tang PY - 2006/05/10/ UR - http://dx.doi.org/10.1016/j.tsf.2005.09.158 ER -