A hardware logic simulation system

@article{citeulike:2616017, abstract = {Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations}, author = {Agrawal, P. and Dally, W. J. }, booktitle = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, citeulike-article-id = {2616017}, doi = {http://dx.doi.org/10.1109/43.45853}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, keywords = {accelerator, simulation}, number = {1}, pages = {19--29}, posted-at = {2008-03-31 13:20:28}, priority = {2}, title = {A hardware logic simulation system}, url = {http://dx.doi.org/10.1109/43.45853}, volume = {9}, year = {1990} }

TY - JOUR ID - citeulike:2616017 L3 - citeulike-article-id:2616017 TI - A hardware logic simulation system T2 - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on JF - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VL - 9 IS - 1 SP - 19 EP - 29 N2 - Multiple-delay logic simulation algorithms developed for the microprogrammable accelerator for rapid simulations (MARS) hardware simulator are discussed. In particular, timing-analysis algorithms for event cancellations, spike and race analyses, and oscillation detection are described. It is shown how a reconfigurable set of processors, called processing elements (PEs), can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned-memory, message-passing architecture of MARS. Three logic simulators-two multiple delay and one unit delay-have been implemented using slightly different configuration of the available PEs. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times that of an Amdahl 5870 system running a production-quality software simulator while retaining the accuracy of simulations KW - accelerator KW - simulation AU - Agrawal, P AU - Dally, WJ PY - 1990/// UR - http://dx.doi.org/10.1109/43.45853 ER -