A digital architecture for support vector machines: theory, algorithm, and FPGA implementation

@article{citeulike:2755715, abstract = {In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance.}, author = {Anguita, D. and Boni, A. and Ridella, S. }, booktitle = {Neural Networks, IEEE Transactions on}, citeulike-article-id = {2755715}, doi = {10.1109/TNN.2003.816033}, journal = {Neural Networks, IEEE Transactions on}, keywords = {dsp\_on\_fpga, fpga}, number = {5}, pages = {993--1009}, posted-at = {2008-05-05 09:38:07}, priority = {2}, title = {A digital architecture for support vector machines: theory, algorithm, and FPGA implementation}, url = {http://dx.doi.org/10.1109/TNN.2003.816033}, volume = {14}, year = {2003} }

TY - JOUR ID - citeulike:2755715 L3 - citeulike-article-id:2755715 TI - A digital architecture for support vector machines: theory, algorithm, and FPGA implementation T2 - Neural Networks, IEEE Transactions on JF - Neural Networks, IEEE Transactions on VL - 14 IS - 5 SP - 993 EP - 1009 N2 - In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance. KW - dsp_on_fpga KW - fpga AU - Anguita, D AU - Boni, A AU - Ridella, S PY - 2003/// UR - http://dx.doi.org/10.1109/TNN.2003.816033 ER -