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alagor library [55 articles]

最近 alagor さんのライブラリ .
  • Perfect Simulations for Random Trip Mobility Models
    posted to no-tag by alagor on 2007-11-29 06:58:23 as **
  • palm05.pdf (application/pdf Object)
    posted to no-tag by alagor on 2007-11-29 06:57:02 as **
  • A Fuzzy Cache Replacement Policy and Its Experimental Performance Assessment
    Innovations in Information Technology, 2006 (2006), pp. 1-5.
    by Sedigheh Khajoueinejad, Mojtaba Sabeghi, Azam Sadeghzadeh
    posted to caching fuzzy logic management memory by alagor on 2007-11-06 19:40:27 as ***
  • Defending against flooding-based distributed denial-of-service attacks: a tutorial
    Communications Magazine, IEEE, Vol. 40, No. 10. (2002), pp. 42-51.
    by RKC Chang
    posted to crowds denial dos flash flooding of service by alagor on 2007-10-28 20:29:00 as ** along with 1 person network01
  • Extended Dominating Set and Its Applications in Ad Hoc Networks Using Cooperative Communication
    Parallel and Distributed Systems, IEEE Transactions on, Vol. 17, No. 8. (2006), pp. 851-864.
    by Jie Wu, M Cardei, Fei Dai, Shuhui Yang
    posted to no-tag by alagor on 2007-03-01 05:49:41 as **
  • Filecules in High-Energy Physics: Characteristics and Impact on Resource Management
    High Performance Distributed Computing, 2006 15th IEEE International Symposium on (2006), pp. 69-80.
    by A Iamnitchi, G Garzoglio, S Doraimani
    posted to no-tag by alagor on 2006-12-12 21:31:11 as ** along with 1 person ahgharaibeh
  • Benchmark probes for grid assessment
    Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International (2004), 276.
    by G Chun, H Dail, H Casanova, A Snavely
    posted to no-tag by alagor on 2006-12-12 20:56:08 as **
  • Thermal Modeling of Multi-Core Processors
    Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on (2006), pp. 96-100.
    by Guoping Xu
    posted to core multi processor temperature by alagor on 2006-11-27 13:26:28 as **
  • Multi-core to the masses
    Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on (2005), 3.
    by J Rattner
    posted to no-tag by alagor on 2006-11-27 13:08:49 as **
  • Route packets, not wires: on-chip interconnection networks
    Design Automation Conference, 2001. Proceedings (2001), pp. 684-689.
    by WJ Dally, B Towles
    posted to chip networks on by alagor on 2006-11-26 21:42:00 as *****
  • Design of databus charge recovery mechanism
    ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International (2000), pp. 283-287.
    by V Lyuboslavsky, B Bishop, V Narayanan, MJ Irwin
    posted to no-tag by alagor on 2006-11-26 20:03:42 as **
  • Power consumption estimation in CMOS VLSI chips
    Solid-State Circuits, IEEE Journal of, Vol. 29, No. 6. (1994), pp. 663-670.
    by Dake Liu, C Svensson
    posted to interconnect low power by alagor on 2006-11-26 19:04:04 as ** along with 1 person Pepijn
  • Conditional techniques for low power consumption flip-flops
    Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, Vol. 2 (2001), pp. 803-806 vol.2.
    by N Nedovic, M Aleksic, VG Oklobdzija
    posted to flip flops low-power by alagor on 2006-11-26 16:43:07 as *
  • Conditional-capture flip-flop for statistical power reduction
    Solid-State Circuits, IEEE Journal of, Vol. 36, No. 8. (2001), pp. 1263-1271.
    by Bai-Sun Kong, Sam-Soo Kim, Young-Hyun Jun
    posted to flip flops low-power by alagor on 2006-11-26 16:40:17 as *
  • New clock-gating techniques for low-power flip-flops
    Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on (2000), pp. 114-119.
    by AGM Strollo, E Napoli, D De Caro
    posted to consumption flip flops low-power power by alagor on 2006-11-26 14:57:37 as ***
  • Multiple Instruction Stream Processor
    (2006), pp. 114-127.
    by Richard A Hankins, Gautham N Chinya, Jamison D Collins, Perry H Wang, Ryan Rakvic, Hong Wang, John P Shen
    posted to consumption economical efficiency microprocessor pentium performance power by alagor on 2006-11-26 14:52:29 as *****
  • Why Intel is designing multi-core processors
    (2006), pp. 113-113.
    by Geoff Lowney
    posted to consumption economical efficiency microprocessor pentium performance power by alagor on 2006-11-26 14:51:34 as *****
  • Multi-Core Processors: New Way to Achieve High System Performance
    Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006. International Symposium on (2006), pp. 9-13.
    by P Gepner, MF Kowalik
    posted to consumption performance power by alagor on 2006-11-26 14:49:37 as *****
  • Low-voltage swing clock distribution schemes
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Vol. 4 (2001), pp. 418-421 vol. 4.
    by QK Zhu, M Zhang
    posted to clock half swinging by alagor on 2006-11-25 23:39:26 as **
  • Half-swing clocking scheme for 75% power saving in clocking circuitry
    Solid-State Circuits, IEEE Journal of, Vol. 30, No. 4. (1995), pp. 432-435.
    by H Kojima, S Tanaka, K Sasaki
    posted to clock half scheme swinging by alagor on 2006-11-25 22:20:45 as **
  • Transistor level budgeting for power optimization
    Quality Electronic Design, 2004. Proceedings. 5th International Symposium on (2004), pp. 116-121.
    by E Kursun, S Ghiasi, M Sarrafzadeh
    posted to reordering transistor by alagor on 2006-11-25 21:37:14 as **
  • Effects of transistor reordering on the performance of MOS digital circuits
    Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on (1992), pp. 121-124 vol.1.
    by BS Carlson, CYR Chen
    posted to reordering transistor by alagor on 2006-11-25 21:23:59 as **
  • Performance enhancement of CMOS VLSI circuits by transistor reordering
    (1993), pp. 361-366.
    by Bradley S Carlson, Roger CY Chen
    posted to reordering transistor by alagor on 2006-11-25 21:01:14 as **
  • Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
    (1995), pp. 167-172.
    by Manjit Borah, Robert M Owens, Mary J Irwin
    posted to sizing transistor by alagor on 2006-11-25 20:27:21 as ***
  • Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits
    Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Vol. 3 (2000), pp. 291-294 vol.3.
    by A Wroblewski, CV Schimpfle, JA Nossek
    posted to sizing transistor by alagor on 2006-11-25 19:37:43 as *
  • Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm
    System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on (2005), pp. 283-288.
    by N Masoumi, J Ghasemi, M Ahmadian, F Raissi, M Masoumi
    posted to sizing transistor by alagor on 2006-11-25 19:36:18 as *
  • Logical path delay distribution and transistor sizing
    IEEE-NEWCAS Conference, 2005. The 3rd International (2005), pp. 391-394.
    by A Kabbani, D Al-Khalili, AJ Al-Khalili
    posted to sizing transistor by alagor on 2006-11-25 19:35:49 as *
  • Transistor sizing for high performance and low power
    Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997 (1997), pp. 591-594.
    by JP Fishburn, S Taneja
    posted to sizing transistor by alagor on 2006-11-25 19:32:40 as *
  • Transistor sizing: how to control the speed and energy consumption of a circuit
    Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on (2004), pp. 51-61.
    by J Ebergen, J Gainsley, P Cunningham
    posted to cmos consumption power solutions transistor by alagor on 2006-11-25 19:25:35 as ** along with 1 person tritan
  • Low power design challenges for the decade (invited talk)
    (2001), pp. 293-296.
    by Shekhar Borkar
    posted to cmos consumption management microprocessor power by alagor on 2006-11-25 18:56:09 as **
  • Technology and design challenges for low power and high performance [microprocessors]
    Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on (1999), pp. 163-168.
    by V De, S Borkar
    posted to cmos consumption power scaling transistor by alagor on 2006-11-23 16:54:11 as **
  • Thermal runaway in integrated circuits
    Device and Materials Reliability, IEEE Transactions on, Vol. 6, No. 2. (2006), pp. 300-305.
    by A Vassighi, M Sachdev
    posted to cmos consumption power by alagor on 2006-11-23 16:14:10 as **
  • CMOS scaling for high performance and low power-the next ten years
    Proceedings of the IEEE, Vol. 83, No. 4. (1995), pp. 595-606.
    by B Davari, RH Dennard, GG Shahidi
    posted to cmos consumption microprocessor by alagor on 2006-11-23 15:10:51 as **
  • Exploring the limits of leakage power reduction in caches
    ACM Trans. Archit. Code Optim., Vol. 2, No. 3. (September 2005), pp. 221-246.
    by Yan Meng, Timothy Sherwood, Ryan Kastner
    posted to consumption efficiency power solutions by alagor on 2006-11-23 14:55:54 as *
  • A dynamic voltage scaled microprocessor system
    Solid-State Circuits, IEEE Journal of, Vol. 35, No. 11. (2000), pp. 1571-1580.
    by TD Burd, TA Pering, AJ Stratakos, RW Brodersen
    posted to management power by alagor on 2006-11-23 12:16:39 as read along with 1 person hannibal_07
  • Minimizing power consumption in digital CMOS circuits
    Proceedings of the IEEE, Vol. 83, No. 4. (1995), pp. 498-523.
    by AP Chandrakasan, RW Brodersen
    posted to management power by alagor on 2006-11-22 20:41:28 as **** along with 1 person gorker
  • Managing the Impact of Increasing Microprocessor Power Consumption
    Intel Technology Journal, Vol. 5, No. 1. (2001)
    by S Gunther, F Binns, DM Carmean, JC Hall
    posted to consumption pentium power by alagor on 2006-11-22 19:34:55 as **
  • The Inevitability of Reconfigurable Systems
    Queue, Vol. 1, No. 7. (October 2003), pp. 34-43.
    by Nick Tredennick, Brion Shimamoto
    posted to consumption management power by alagor on 2006-11-22 16:47:06 as **
  • Modern System Power Management
    Queue, Vol. 1, No. 7. (October 2003), pp. 66-72.
    by Andrew Grover
    posted to consumption management power by alagor on 2006-11-22 16:46:27 as read
  • Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law
    Queue, Vol. 1, No. 7. (October 2003), pp. 26-33.
    by Shekhar Borkar
    posted to consumption law moores power by alagor on 2006-11-22 16:45:11 as **
  • Making a Case for Efficient Supercomputing
    Queue, Vol. 1, No. 7. (October 2003), pp. 54-64.
    by Wu-Chun Feng
    posted to consumption economical efficiency microprocessor power solutions supercomputer by alagor on 2006-11-22 16:43:27 as read
  • Power and performance optimization at the system level
    (2005), pp. 125-132.
    by Valentina Salapura, Randy Bickford, Matthias Blumrich, Arthur A Bright, Dong Chen, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta, Shawn Hall, Ruud A Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V Kopcsay, Martin Ohmacht, Rick A Rand, Todd Takken, Pavlos Vranas
    posted to consumption efficiency microprocessor power solutions by alagor on 2006-11-22 16:34:15 as **
  • Using multiple energy gears in MPI programs on a power-scalable cluster
    (2005), pp. 164-173.
    by Vincent W Freeh, David K Lowenthal
    posted to consumption efficiency microprocessor power solutions by alagor on 2006-11-22 16:33:24 as **
  • Future processors: flexible and modular
    (2005), pp. 4-6.
    by Charlie Johnson, Jeff Welser
    posted to consumption efficiency microprocessor power solutions by alagor on 2006-11-22 16:31:19 as *** along with 1 person gantlord
  • Interconnect-Aware Coherence Protocols for Chip Multiprocessors
    (2006), pp. 339-351.
    by Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B Carter
    posted to consumption efficiency microprocessor power solutions by alagor on 2006-11-22 16:29:51 as **
  • Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
    (2005), pp. 310-321.
    by Emil Talpes, Diana Marculescu
    posted to consumption efficiency power solutions by alagor on 2006-11-22 16:26:31 as **
  • Implementing low-power configurable processors: practical options and tradeoffs
    (2005), pp. 706-711.
    by John Wei, Chris Rowen
    posted to consumption efficiency power solutions by alagor on 2006-11-22 16:25:12 as **
  • Hierarchical power management with application to scheduling
    (2005), pp. 269-274.
    by Peng Rong, Massoud Pedram
    posted to consumption efficiency power solutions by alagor on 2006-11-22 16:24:14 as **
  • Runtime identification of microprocessor energy saving opportunities
    (2005), pp. 275-280.
    by WL Bircher, M Valluri, J Law, LK John
    posted to consumption efficiency power solutions by alagor on 2006-11-22 16:23:21 as **
  • Power reduction techniques for microprocessor systems
    ACM Comput. Surv., Vol. 37, No. 3. (September 2005), pp. 195-237.
    by Vasanth Venkatachalam, Michael Franz
    posted to consumption efficiency power solutions by alagor on 2006-11-22 16:21:11 as *****
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