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タグ: for_thesis [39 articles]

Recent papers classified by the tag for_thesis.
  • SIS: A system for sequential circuit synthesis
    (1992)
    by EM Sentovich, KJ Singh, L Lavagno, C Moon, R Murgai, A Saldanha, H Savoj, PR Stephan, RK Brayton, Sangiovanni A Vincentelli
    posted to for_thesis fpl_paper fpt_paper logic_synthesis synthesis vlsi by nathalie on 2006-06-20 23:21:57 as **
  • High-performance carry chains for FPGAs
    (1998), pp. 223-233.
    by Scott Hauck, Matthew M Hosler, Thomas W Fry
    posted to adder altera architecture arithmetic for_thesis fpga fpl_paper printed by nathalie on 2005-12-07 20:07:41 as ***
  • A survey of power estimation techniques in VLSI circuits
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 2, No. 4. (1994), pp. 446-455.
    by FN Najm
    posted to vlsi for_thesis power power_estimation printed probability by nathalie on 2006-08-30 04:23:09 as read along with 1 person ceegrs2
  • Practical Low Power Digital VLSI Design
    (01 August 1997)
    by Gary K Yeap
    posted to activity for_thesis lag_one power power_estimation probability transition_density vlsi by nathalie on 2006-08-31 00:49:32 as ** along with 1 person philip-eecs
  • Dynamic power consumption in Virtex&\#8482;-II FPGA family
    (2002), pp. 157-164.
    by Li Shang, Alireza S Kaviani, Kusuma Bathala
    posted to for_thesis fpga fpl_paper power power_estimation power_measurement printed xilinx by nathalie on 2005-05-13 00:09:54 as ** along with 1 person ceegrs2
  • Information theoretic measures for power analysis [logic design]
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 15, No. 6. (1996), pp. 599-610.
    by D Marculescu, R Marculescu, M Pedram
    posted to for_thesis fpl_paper power power_estimation printed by nathalie on 2006-03-11 07:01:07 as **
  • Fundamentals of Digital Logic with Verilog Design
    (20 August 2002)
    by Stephen Brown, Zvonko Vranesic
    posted to altera digital_logic for_thesis fpga by nathalie on 2006-08-29 06:31:28 as **
  • Architecture of field-programmable gate arrays
    Proceedings of the IEEE, Vol. 81, No. 7. (1993), pp. 1013-1029.
    by J Rose, El, A Sangiovanni-Vincentelli
    posted to architecture for_thesis fpga by nathalie on 2006-04-25 23:33:19 as **
  • Switching Activity Analysis Considering Spatioternporal Correlations
    Computer-Aided Design, 1994., IEEE/ACM International Conference on (1994), pp. 294-299.
    by R Marculescu, D Marculescu, M Pedram
    posted to activity for_thesis lag_one power power_estimation probability transition_density by nathalie on 2006-08-31 00:26:37 as **
  • Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs
    Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 (1999), pp. 191-194.
    by SD Haynes, AB Ferrari, PYK Cheung
    posted to altera architecture arithmetic for_thesis fpga fpl_paper multiplier printed xilinx by nathalie on 2005-06-22 06:32:37 as **
  • High-Level Power Analysis and Optimization
    (30 November 1997)
    by Anand Raghunathan, Niraj K Jha, Sujit Dey
    posted to for_thesis fpl_paper power power_estimation synthesis by nathalie on 2006-03-11 05:49:23 as **
  • Overview of the FREEDOM compiler for mapping DSP software to FPGAs
    Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on (2004), pp. 37-46.
    by D Zaretsky, M Mittal, Xiaoyong Tang, P Banerjee
    posted to arithmetic dsp for_thesis fpga fpl_paper printed xilinx by nathalie on 2006-02-10 19:29:03 as **
  • A verilog RTL synthesis tool for heterogeneous FPGAs
    Field Programmable Logic and Applications, 2005. International Conference on (2005), pp. 305-310.
    by P Jamieson, J Rose
    posted to altera arithmetic coarse_grained_architectures dsp for_thesis fpga fpl_paper logic_synthesis printed synthesis technology_mapping by nathalie on 2006-02-19 21:11:59 as read
  • Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation
    (1999)
    by Janardhan H Satyanarayana, Keshab K Parhi
    posted to arithmetic dsp for_thesis multiplier power power_estimation by nathalie on 2006-04-18 16:58:07 as **
  • Power modeling and characteristics of field programmable gate arrays
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 24, No. 11. (2005), pp. 1712-1724.
    by Fei Li, Y Lin, Lei He, Deming Chen, J Cong
    posted to for_thesis fpga power power_estimation printed by nathalie on 2006-04-27 19:43:42 as ***** along with 1 person ceegrs2
  • A new generation of digital VLSI CAD tools based on probability
    System Theory, 1995., Proceedings of the Twenty-Seventh Southeastern Symposium on (1995), pp. 348-352.
    by N Abdallah, J Dunoyer, PB Sabet
    posted to actel for_thesis printed probability transition_density vlsi by nathalie on 2006-08-11 00:27:04 as **
  • Power-aware Technology Mapping for LUT-based FPGAs
    Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on (2002), pp. 211-218.
    by JH Anderson, FN Najm
    posted to activity algorithms for_thesis fpl_paper fpt_paper logic_synthesis lut power power_estimation probability technology_mapping xilinx by nathalie on 2006-09-01 06:55:25 as ** along with 1 person ceegrs2
  • Dynamic Voltage Scaling for Commercial FPGAs
    Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology (2005), pp. 173-180.
    by CT Chow, LSM Tsui, PHW Leong, W Luk, SJE Wilton
    posted to altera architecture for_thesis fpga fpl_paper fpt_paper power power_estimation vlsi xilinx by nathalie on 2006-09-01 06:46:27 as ** along with 2 people reactgary ceegrs2
  • A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure
    FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 226-234.
    by SD Haynes, PYK Cheung
    posted to altera architecture arithmetic embedded for_thesis fpga fpl_paper image_processing multiplier printed xilinx by nathalie on 2006-01-10 23:48:14 as read
  • There is Life Left in ASICs
    (2003), pp. 48-50.
    by Leon Stok, John Cohn
    posted to asic for_thesis fpga power vlsi by nathalie on 2006-09-01 01:05:13 as ** along with 1 person ceegrs2
  • Architectural power analysis: The dual bit type method
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 3, No. 2. (1995), pp. 173-187.
    by PE Landman, JM Rabaey
    posted to adder architecture arithmetic for_thesis fpl_paper multiplier power power_estimation printed by nathalie on 2006-03-05 02:24:58 as read along with 1 person ceegrs2
  • Directional and single-driver wires in FPGA interconnect
    Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (2004), pp. 41-48.
    by G Lemieux, E Lee, M Tom, A Yu
    posted to altera architecture for_thesis fpga interconnect routing xilinx by nathalie on 2006-08-28 04:10:16 as **
  • Power-aware RAM Mapping for FPGA Embedded Memory Blocks
    (2006), pp. 189-198.
    by Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
    posted to activity algorithms altera for_thesis fpga logic_synthesis memory power by nathalie on 2006-09-01 05:55:51 as ** along with 1 person ceegrs2
  • An FPGA architecture with enhanced datapath functionality
    (2003), pp. 195-204.
    by Katarzyna Leijten-Nowak, Jef L van Meerbergen
    posted to architecture arithmetic dsp for_thesis fpga fpl_paper printed by nathalie on 2006-02-16 21:05:42 as read
  • Measuring the Gap Between FPGAs and ASICs
    (2006), pp. 21-30.
    by Ian Kuon, Jonathan Rose
    posted to altera area asic benchmarks for_thesis fpga leakage performance power xilinx by nathalie on 2006-09-01 05:24:19 as ** along with 2 people JonsonXP ceegrs2
  • Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
    (2002), pp. 667-676.
    by Tony Stansfield
    posted to architecture area arithmetic for_thesis fpga lut reconfigurable_computing routing by nathalie on 2006-09-05 06:44:28 as **
  • A 90nm Low-power FPGA for Battery-powered Applications
    (2006), pp. 3-11.
    by Tim Tuan, Sean Kao, Arif Rahman, Satyaki Das, Steve Trimberger
    posted to architecture for_thesis fpga leakage power xilinx by nathalie on 2006-09-01 05:17:34 as ** along with 1 person ceegrs2
  • A New Switch Block for Segmented FPGAs
    (1999), pp. 274-281.
    by Imran M Masud, Steven JE Wilton
    posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:24:42 as **
  • Universal switch modules for FPGA design
    ACM Trans. Des. Autom. Electron. Syst., Vol. 1, No. 1. (January 1996), pp. 80-101.
    by Yao-Wen Chang, DF Wong, CK Wong
    posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:21:38 as **
  • FPGA Power Reduction Using Configurable Dual-Vdd
    Design Automation Conference, 2004. Proceedings. 41st (2004), pp. 735-740.
    by Fei Li, Yan Lin, Lei He
    posted to architecture for_thesis fpga leakage power spice vlsi by nathalie on 2006-09-01 04:59:15 as ** along with 1 person ceegrs2
  • On two-step routing for FPGAS
    (1997), pp. 60-66.
    by Guy GF Lemieux, Stephen D Brown, Daniel Vranesic
    posted to architecture for_thesis interconnect routing xilinx by nathalie on 2006-08-11 06:12:00 as **
  • notes High-level power modeling, estimation, and optimization
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 17, No. 11. (1998), pp. 1061-1079.
    by E Macii, M Pedram, F Somenzi
    posted to for_thesis power power_estimation printed by nathalie on 2006-03-05 06:30:58 as *****
  • The "quiet" state-a new approach to low-power multiplier design
    Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, Vol. 2 (2003), pp. 2222-2226 Vol.2.
    by N Mallios, N Burgess
    posted to activity arithmetic for_thesis multiplier power by nathalie on 2006-10-02 05:07:12 as **
  • notes Active Leakage Power Optimization for FPGAs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 3. (2006), pp. 423-437.
    by JH Anderson, FN Najm
    posted to algorithms for_thesis fpga leakage lut power xilinx by nathalie on 2006-09-01 02:18:26 as ** along with 1 person ceegrs2
  • Architecture and CAD for Deep-Submicron FPGAs (The International Series in Engineering and Computer Science)
    (31 March 1999)
    by Vaughn Betz, Jonathan Rose, Alexander Marquardt
    posted to architecture for_thesis fpga placement routing by nathalie on 2006-04-25 18:34:18 as ** along with 1 person JonsonXP
  • The Design of a Low Energy FPGA
    Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on (1999), pp. 188-193.
    by V George, Hui Zhang, J Rabaey
    posted to architecture for_thesis fpga interconnect lut power power_estimation power_measurement routing xilinx by nathalie on 2006-09-01 01:45:28 as **
  • notes The RAW benchmark suite: computation structures for general purpose computing
    FPGAs for Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on (1997), pp. 134-143.
    by J Babb, M Frank, V Lee, E Waingold, R Barua, M Taylor, J Kim, S Devabhaktuni, A Agarwal
    posted to architecture benchmarks for_thesis fpga fpt_paper integer matrix reconfigurable_computing by nathalie on 2006-05-16 23:44:16 as **
  • Transition density: a new measure of activity in digital circuits
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 12, No. 2. (1993), pp. 310-323.
    by FN Najm
    posted to activity for_thesis fpl_paper fpt_paper power_estimation printed transition_density vlsi by nathalie on 2006-07-06 19:31:29 as **
  • Power Estimation Techniques for FPGAs
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10. (2004), pp. 1015-1027.
    by JH Anderson, FN Najm
    posted to activity for_thesis fpga interconnect power power_estimation vlsi xilinx by nathalie on 2006-09-01 01:12:59 as ** along with 1 person ceegrs2
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